A hardware/software partitioning algorithm for processor cores of digital signal processing

Nozomu Togawa*, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A hardware/software cosynthesis system for processor cores of digital signal processing has been developed. This paper focuses on a hardware/software partitioning algorithm which is one of the key issues in the system. Given an input assembly code generated by the compiler in the system, the proposed hardware/software partitioning algorithm first determines the types and the numbers of required hardware units, such as multiple functional units, hardware loop units, and particular addressing units, for a processor core (initial resource allocation). Second, the hardware units determined at initial resource allocation are reduced one by one while the assembly code meets a given timing constraint (configuration of a processor core). The execution time of the assembly code becomes longer but the hardware costs for a processor core to execute it becomes smaller. Finally, it outputs an optimized assembly code and a processor configuration. Experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program/data.

本文言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
出版社Institute of Electrical and Electronics Engineers Inc.
ページ335-338
ページ数4
ISBN(電子版)078035012X
DOI
出版ステータスPublished - 1999
イベント4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong
継続期間: 1999 1 181999 1 21

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
1999-January

Conference

Conference4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
国/地域Hong Kong
CityWanchai
Period99/1/1899/1/21

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計

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