A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

    研究成果: Article

    2 引用 (Scopus)

    抄録

    This letter proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions and a timing constraint, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume for each operation type a super SIMD functional unit which can execute all the SIMD instructions. Secondly we reduce a SIMD instruction or "sub-function" of each super functional unit, one by one, while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally find SIMD functional unit configuration as well as a processor core architecture. The promising experimental results are also shown.

    元の言語English
    ページ(範囲)3218-3224
    ページ数7
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E86-A
    発行部数12
    出版物ステータスPublished - 2003 12

    Fingerprint

    Hardware/software Partitioning
    Hardware
    Unit
    Timing
    Configuration
    Update
    Experimental Results

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    これを引用

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    AU - Tachikake, Koichi

    AU - Miyaoka, Yuichiro

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

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