A heuristic method for module sizing under fixed-outline constraints

Xiaolin Zhang, Song Chen, Longfan Piao, Takeshi Yoshimura

研究成果: Conference contribution

抄録

In this paper, a heuristic method for module sizing is proposed as a post-processing of the fixed-outline floorplanning. The heuristic method is based on horizontal and vertical slacks of blocks In the floorplan. By evaluating the distances of each block to the chip boundaries, x-slack and y-slack can be calculated. On the one hand, the heuristic focuses on the blocks has non-zero x-slack or non-zero y-slack but not both. These blocks will be first sorted by the amount of x / y-slack. The block having the most slack will be selected and reshaped, it has a potential to reduce the fixed-outline violation. On the other hand, the heuristic makes use of a marked flag for each block. After reshaping the block, the marked flag of the block will be set to 1. The slack of all the blocks will be recomputed and the focused blocks with marked flag 0 are reselected and sorted. If the set offocused blocks with marked flag 0 is empty, the marked flag of all the blocks will be reset to 0 and repeat the previous steps. If the fixed-outline constraint is not satisfied, we will repeat the procedure with defined maximum iteration number. Experimental results show that, the proposed heuristic could efficient achieve highly success rate without sacrificing much wire-length.

本文言語English
ホスト出版物のタイトルASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
ページ738-741
ページ数4
DOI
出版ステータスPublished - 2009
イベント2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
継続期間: 2009 10 202009 10 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CityChangsha
Period09/10/2009/10/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

フィンガープリント 「A heuristic method for module sizing under fixed-outline constraints」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル