In this paper, a heuristic method for module sizing is proposed as a post-processing of the fixed-outline floorplanning. The heuristic method is based on horizontal and vertical slacks of blocks In the floorplan. By evaluating the distances of each block to the chip boundaries, x-slack and y-slack can be calculated. On the one hand, the heuristic focuses on the blocks has non-zero x-slack or non-zero y-slack but not both. These blocks will be first sorted by the amount of x / y-slack. The block having the most slack will be selected and reshaped, it has a potential to reduce the fixed-outline violation. On the other hand, the heuristic makes use of a marked flag for each block. After reshaping the block, the marked flag of the block will be set to 1. The slack of all the blocks will be recomputed and the focused blocks with marked flag 0 are reselected and sorted. If the set offocused blocks with marked flag 0 is empty, the marked flag of all the blocks will be reset to 0 and repeat the previous steps. If the fixed-outline constraint is not satisfied, we will repeat the procedure with defined maximum iteration number. Experimental results show that, the proposed heuristic could efficient achieve highly success rate without sacrificing much wire-length.
|ホスト出版物のタイトル||ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC|
|出版ステータス||Published - 2009|
|イベント||2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha|
継続期間: 2009 10 20 → 2009 10 23
|Other||2009 8th IEEE International Conference on ASIC, ASICON 2009|
|Period||09/10/20 → 09/10/23|
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