A high efficiency and high linearity power amplifier utilizing postlinearization technique for 5.8 GHz DSRC applications

Qing Liu, Sun Jiangtao, Yong Ju Shu, Koji Horie, Nobuyuki Itoh, Toshihiko Yoshimasu

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

In this paper, a post-linearization technique of cascode CMOS power amplifier is presented. The proposed method adopts two cascode FET, one operates in class AB mode and the other works near class B mode, which absorbs the nonlinear current of third-order intermodulation distortion (IMD). The proposed method is investigated for 5.8 GHz Dedicated Short Range Communication (DSRC) applications, and fabricated by 0.13 μm CMOS process. The measured results show that the proposed power amplifier exhibited a power gain of 11.5 dB, an output power of 1 dB compression point (P1dB) of 17.3 dBm, a power added efficiency (PAE) of 32% at P1dB with a low voltage operation of 2.0 V. The improvement in IMD of 6 dB over large output power range and a maximum improvement of 12 dB were achieved.

本文言語English
ホスト出版物のタイトル2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011
ページ45-48
ページ数4
DOI
出版ステータスPublished - 2011
イベント2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011 - Phoenix, AZ, United States
継続期間: 2011 1 162011 1 19

出版物シリーズ

名前2011 IEEE Radio and Wireless Week, RWW 2011 - 2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011

Conference

Conference2011 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011
CountryUnited States
CityPhoenix, AZ
Period11/1/1611/1/19

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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