A high-level energy-optimizing algorithm for system VLSIs based on area/time/power estimation

Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Article査読

抄録

This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

本文言語English
ページ(範囲)2655-2666
ページ数12
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E85-A
12
出版ステータスPublished - 2002 12

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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