A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering

Qian Xie*, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto

*この研究の対応する著者

    研究成果: Conference contribution

    3 被引用数 (Scopus)

    抄録

    This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs 12-24 clock cycles per iteration for different code rates. Compared with the state-of-art work, this decoder reduces total memory bits to a great extent and achieves 2x-4.3x higher parallelism with 1.2x hardware cost. The synthesis result proves the low power potential of this architecture.

    本文言語English
    ホスト出版物のタイトル2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
    ページ122-127
    ページ数6
    DOI
    出版ステータスPublished - 2011
    イベント2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut
    継続期間: 2011 10 42011 10 7

    Other

    Other2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
    CityBeirut
    Period11/10/411/10/7

    ASJC Scopus subject areas

    • 信号処理

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