A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n+ poly gate and a surface channel PMOS with p+ poly gate whose source/drain and gate were salicided with low-resistance TiSi2. The gate/n- overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.
|ジャーナル||Technical Digest - International Electron Devices Meeting|
|出版ステータス||Published - 1989 12月 1|
|イベント||1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA|
継続期間: 1989 12月 3 → 1989 12月 6
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