A high-performance CABAC encoder architecture for HEVC and H.264/AVC

Jinjia Zhou, Dajiang Zhou, Wei Fei, Satoshi Goto

研究成果: Conference contribution

14 引用 (Scopus)

抜粋

This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%∼34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dualstandard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27∼4.40 bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.

元の言語English
ホスト出版物のタイトル2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings
ページ1568-1572
ページ数5
DOI
出版物ステータスPublished - 2013
イベント2013 20th IEEE International Conference on Image Processing, ICIP 2013 - Melbourne, VIC
継続期間: 2013 9 152013 9 18

Other

Other2013 20th IEEE International Conference on Image Processing, ICIP 2013
Melbourne, VIC
期間13/9/1513/9/18

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

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  • これを引用

    Zhou, J., Zhou, D., Fei, W., & Goto, S. (2013). A high-performance CABAC encoder architecture for HEVC and H.264/AVC. : 2013 IEEE International Conference on Image Processing, ICIP 2013 - Proceedings (pp. 1568-1572). [6738323] https://doi.org/10.1109/ICIP.2013.6738323