A high-performance circuit design algorithm using data dependent approximation

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

    研究成果: Conference contribution

    抄録

    This paper proposes a high-performance circuit design algorithm using input data dependent approximation. In our algorithm, STEPCs (Suspicious Timing Error Prediction Circuits) are utilized for identifying the paths to be optimized inside a circuit efficiently. Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 11.1% within the error rate of 2.1% compared to a conventional design technique.

    本文言語English
    ホスト出版物のタイトルISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ95-96
    ページ数2
    ISBN(電子版)9781467393089
    DOI
    出版ステータスPublished - 2016 12 27
    イベント13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
    継続期間: 2016 10 232016 10 26

    Other

    Other13th International SoC Design Conference, ISOCC 2016
    CountryKorea, Republic of
    CityJeju
    Period16/10/2316/10/26

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Instrumentation

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