A high performance LDPC decoder for IEEE802.11n standard

Wen Jit, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

抄録

In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

本文言語English
ホスト出版物のタイトルProceedings of the ASP-DAC 2009
ホスト出版物のサブタイトルAsia and South Pacific Design Automation Conference 2009
ページ127-128
ページ数2
DOI
出版ステータスPublished - 2009 4 20
イベントAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan
継続期間: 2009 1 192009 1 22

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

ConferenceAsia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
CountryJapan
CityYokohama
Period09/1/1909/1/22

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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