A high performance partially-parallel irregular LDPC decoder based on sum-delta message passing schedule

Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

研究成果: Article査読

2 被引用数 (Scopus)

抄録

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.1 In standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations, (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost, (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

本文言語English
ページ(範囲)3622-3629
ページ数8
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E91-A
12
DOI
出版ステータスPublished - 2008 1 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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