A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.
|出版ステータス||Published - 1990 12月 1|
|イベント||1990 Symposium on VLSI Circuits - Honolulu, HI, USA|
継続期間: 1990 6月 7 → 1990 6月 9
|Other||1990 Symposium on VLSI Circuits|
|City||Honolulu, HI, USA|
|Period||90/6/7 → 90/6/9|
ASJC Scopus subject areas