In this paper, a high speed deblocking filter architecture for H.264/AVC is proposed to process one macroblock in 48 clock cycles and give real-time support to QFHD (3840x2160)@60fps sequences at less than 100MHz. 4 edge filters organized in 2 groups for simultaneously processing vertical and horizontal edges are applied in this architecture to enhance its throughput. While parallelism increases, pipeline hazards arise owing to the latency of edge filters and data dependency of deblocking algorithm. To solve this problem, a zig-zag processing schedule is proposed to eliminate the pipeline bubbles. Data path of the architecture is then derived according to the processing schedule and optimized through data flow merging, so as to minimize the cost of logic and internal buffer. Meanwhile, the architecture's data input rate is designed to be identical to its throughput, while the transmission order of input data can also match the zig-zag processing schedule. Therefore no intercommunication buffer is required between the deblocking filter and its previous component for speed matching or data reordering. As a result, only one 24x64 two-port SRAM as internal buffer is required in this design. When synthesized with SMIC 130nm process, the architecture costs a gate count of 30.2k, which is competitive considering its high performance.
|ホスト出版物のタイトル||2009 International SoC Design Conference, ISOCC 2009|
|出版ステータス||Published - 2009|
|イベント||2009 International SoC Design Conference, ISOCC 2009 - Busan|
継続期間: 2009 11月 22 → 2009 11月 24
|Other||2009 International SoC Design Conference, ISOCC 2009|
|Period||09/11/22 → 09/11/24|
ASJC Scopus subject areas