A high-speed trace-driven cache configuration simulator for dual-core processor L1 caches

    研究成果: Article

    抄録

    Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach.

    元の言語English
    ページ(範囲)1283-1292
    ページ数10
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E96-A
    発行部数6
    DOI
    出版物ステータスPublished - 2013 6

    Fingerprint

    Cache
    Data structures
    Simulator
    High Speed
    Simulators
    Trace
    Application programs
    Embedded systems
    Configuration
    Cache memory
    Data Structures
    Embedded Systems
    Simulation
    Exact Simulation
    Associativity
    Multi-core Processor
    Experimental Results
    Theorem
    Demonstrate

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    これを引用

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    abstract = "Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach.",
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    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

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    KW - Multicore cache

    KW - Optimaize cache memory

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