In this paper, we propose a full hardware encoder architecture for context-based adaptive binary arithmetic coding (CABAC) for Super Hi-vision data that tries to enlarge the throughput of the encoder. CABAC is a crucial part in H.264/AVC main profile that provides a great compression ratio at the expense of high computational complexity. Due to the data dependence between bit-wise processing, the throughput of the encoder is limited. Some techniques have been proposed in the latest encoder architecture designs to improve the speed to meet the need of QFHD or 3DHD applications. While for Super Hi-vision (4320p) case, a throughput of more than 1Gbps is required. While the current designs can only reach a throughput of around 660Mbps. As a result, frame parallelism is a usual but hardware costing way to solve the throughput gap. What's more, frame parallel will also cost frame delay problem, which is crucial in real-time system. This design tries to avoid the frame parallelism and save the power by encoding 4 bins per cycle using only one core, while working at a frequency of 264MHz. The technology used for synthesis is SMIC 90nm. Two main ideas are applied in this design to realize this high throughput.
|ホスト出版物のタイトル||Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011|
|出版ステータス||Published - 2011|
|イベント||2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang|
継続期間: 2011 3月 4 → 2011 3月 6
|Other||2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011|
|Period||11/3/4 → 11/3/6|
ASJC Scopus subject areas