A highly efficient inverse transform architecture for multi-standard HDTV decoder

Hang Zhang, Peilin Liu, Yu Hong, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.

    本文言語English
    ホスト出版物のタイトルASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
    ページ525-528
    ページ数4
    DOI
    出版ステータスPublished - 2009
    イベント2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
    継続期間: 2009 10 202009 10 23

    Other

    Other2009 8th IEEE International Conference on ASIC, ASICON 2009
    CityChangsha
    Period09/10/2009/10/23

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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