A highly parallel architecture for deblocking filter in H.264/AVC

Lingfeng Li*, Satoshi Goto, Takeshi Ikenaga

*この研究の対応する著者

研究成果: Article査読

31 被引用数 (Scopus)

抄録

This paper presents a highly parallel architecture for deblocking filter in H.264/AVC. We adopt various parallel schemes in memory sub-system and datapath. A 2-dimensional parallel memory scheme is employed to support efficient parallel access in both horizontal and vertical directions in order to speed up the whole filtering process. This parallel memory also eliminates the need for a transpose circuit. In the datapath, an algorithm optimization is performed to implement parallel filtering with hardware reuse. Pipeline techniques are also adopted to improve the throughput of filtering operations. Our design is implemented under TSMC 0.18 μm technology. Results show that the core size is 0.82 × 1.13mm2 when the maximum frequency is 230 MHz. Compared to other existing architectures, our design has advantages in both speed and area.

本文言語English
ページ(範囲)1623-1628
ページ数6
ジャーナルIEICE Transactions on Information and Systems
E88-D
7
DOI
出版ステータスPublished - 2005 7

ASJC Scopus subject areas

  • ソフトウェア
  • ハードウェアとアーキテクチャ
  • コンピュータ ビジョンおよびパターン認識
  • 電子工学および電気工学
  • 人工知能

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