A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Zhen Lin*, Yiping Dong, Yan Li, Takahiro Watanabe

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.

本文言語English
ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
ページ616-619
ページ数4
DOI
出版ステータスPublished - 2010 12 1
イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
継続期間: 2010 12 62010 12 9

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
国/地域Malaysia
CityKuala Lumpur
Period10/12/610/12/9

ASJC Scopus subject areas

  • 電子工学および電気工学

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