A hypothesis verification method using a regression tree for semiconductor yield analysis

Hidetaka Tsuda*, Hidehiro Shirai, Masahiro Terabe, Kazuo Hashimoto, Ayumi Shinohara

*この研究の対応する著者

研究成果: Article査読

抄録

Several researchers have reported on regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the root node do not indicate the hypothesized causes of a failure. We propose a method for verifying the hypothesized causes of a failure, which reduces the number of verification hypotheses. This method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying regression tree analysis separately to each set of analysis data, and merging and sorting the attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of regression tree analysis for semiconductor yield. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 183(3): 26-36, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22334

本文言語English
ページ(範囲)26-36
ページ数11
ジャーナルElectrical Engineering in Japan (English translation of Denki Gakkai Ronbunshi)
183
3
DOI
出版ステータスPublished - 2013 5 1
外部発表はい

ASJC Scopus subject areas

  • エネルギー工学および電力技術
  • 電子工学および電気工学

フィンガープリント

「A hypothesis verification method using a regression tree for semiconductor yield analysis」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル