TY - JOUR
T1 - A hypothesis verification method using regression tree for semiconductor yield analysis
AU - Tsuda, Hidetaka
AU - Shirai, Hidehiro
AU - Terabe, Masahiro
AU - Hashimoto, Kazuo
AU - Shinohara, Ayumi
PY - 2011/11/7
Y1 - 2011/11/7
N2 - Several researchers have reported the regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying the regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the route node do not indicate the hypothesized causes of failure. We propose a method for verifying the hypothesized causes of failure, which reduces the number of verification hypotheses. Our method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying the regression tree analysis separately to each set of analysis data, and merging and sorting attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of the regression tree analysis for semiconductor yield.
AB - Several researchers have reported the regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying the regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the route node do not indicate the hypothesized causes of failure. We propose a method for verifying the hypothesized causes of failure, which reduces the number of verification hypotheses. Our method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying the regression tree analysis separately to each set of analysis data, and merging and sorting attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of the regression tree analysis for semiconductor yield.
KW - Attribute
KW - Failure cause identification
KW - Hypothesis verification
KW - Regression tree analysis
KW - Semiconductor
KW - Yield analysis
UR - http://www.scopus.com/inward/record.url?scp=80155204527&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80155204527&partnerID=8YFLogxK
U2 - 10.1541/ieejias.131.1232
DO - 10.1541/ieejias.131.1232
M3 - Article
AN - SCOPUS:80155204527
VL - 131
SP - 1232
EP - 1239
JO - IEEJ Transactions on Industry Applications
JF - IEEJ Transactions on Industry Applications
SN - 0913-6339
IS - 10
ER -