A hypothesis verification method using regression tree for semiconductor yield analysis

Hidetaka Tsuda*, Hidehiro Shirai, Masahiro Terabe, Kazuo Hashimoto, Ayumi Shinohara

*この研究の対応する著者

研究成果: Article査読

2 被引用数 (Scopus)

抄録

Several researchers have reported the regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying the regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the route node do not indicate the hypothesized causes of failure. We propose a method for verifying the hypothesized causes of failure, which reduces the number of verification hypotheses. Our method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying the regression tree analysis separately to each set of analysis data, and merging and sorting attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of the regression tree analysis for semiconductor yield.

本文言語English
ページ(範囲)1232-1239
ページ数8
ジャーナルieej transactions on industry applications
131
10
DOI
出版ステータスPublished - 2011 11 7
外部発表はい

ASJC Scopus subject areas

  • 産業および生産工学
  • 電子工学および電気工学

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