A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

M. Fujii*, K. Nii, H. Makino, S. Ohbayashi, M. Igarashi, T. Kawamura, M. Yokota, N. Tsuda, T. Yoshizawa, T. Tsutsui, N. Takeshita, N. Murata, T. Tanaka, T. Fujiwara, K. Asahina, M. Okada, K. Tomita, M. Takeuchi, H. Shinohara

*この研究の対応する著者

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

本文言語English
ホスト出版物のタイトル2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings
ページ131-134
ページ数4
DOI
出版ステータスPublished - 2007
外部発表はい
イベント2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07 - Bunkyo-ku, Japan
継続期間: 2007 3月 192007 3月 22

出版物シリーズ

名前IEEE International Conference on Microelectronic Test Structures

Other

Other2007 IEEE International Conference on Microelectronic Test Structures, ICMTS '07
国/地域Japan
CityBunkyo-ku
Period07/3/1907/3/22

ASJC Scopus subject areas

  • 電子工学および電気工学

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