A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Multiplication with a large number of digits is heavily used when processing data encrypted by a fully homomorphic encryption, which is a bottleneck in computation time. An algorithm utilizing fast number theoretic transform (FNTT) is known as a high-speed multiplication algorithm and the further speeding up is expected by implementing the FNTT process on an FPGA. A high-level synthesis tool enables efficient hardware implementation even for FNTT with a large number of points. In this paper, we propose a methodology for optimizing the loop structure included in a software description of FNTT so that the performance of the synthesized FNTT processor can be maximized. The loop structure optimization is considered in terms of loop flattening and trip count reduction. We implement a 65,536-point FNTT processor with the loop structure optimization on an FPGA, and demonstrate that it can be executed 6.9 times faster than the execution on a CPU.

本文言語English
ホスト出版物のタイトル2018 19th International Symposium on Quality Electronic Design, ISQED 2018
出版社IEEE Computer Society
ページ106-111
ページ数6
ISBN(電子版)9781538612149
DOI
出版ステータスPublished - 2018 5 9
イベント19th International Symposium on Quality Electronic Design, ISQED 2018 - Santa Clara, United States
継続期間: 2018 3 132018 3 14

出版物シリーズ

名前Proceedings - International Symposium on Quality Electronic Design, ISQED
2018-March
ISSN(印刷版)1948-3287
ISSN(電子版)1948-3295

Other

Other19th International Symposium on Quality Electronic Design, ISQED 2018
国/地域United States
CitySanta Clara
Period18/3/1318/3/14

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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