A low cost and high speed CSD-based symmetric transpose block FIR implementation

研究成果: Conference contribution

4 引用 (Scopus)

抜粋

In this paper, a low cost and high speed CSD-based symmetric transpose block FIR design was proposed for low cost digital signal processing. First, the existing area-efficient CSD-based multiplier was optimized by considering the reusability and the symmetry of coefficients for area reduction. Second, the position of the input register was changed for high speed transpose block FIR processing in which half of the number of required multipliers can be saved. When compared with the existing block FIR designs, the proposed FIR design can increase the data rate from 238.66 MHz to 373.13 MHz while saving 10.89% area and 21.30% energy consumption as well.

元の言語English
ホスト出版物のタイトルProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
出版者IEEE Computer Society
ページ311-314
ページ数4
2017-October
ISBN(電子版)9781509066247
DOI
出版物ステータスPublished - 2018 1 8
イベント12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
継続期間: 2017 10 252017 10 28

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
China
Guiyang
期間17/10/2517/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Ye, J., Shi, Y., Togawa, N., & Yanagisawa, M. (2018). A low cost and high speed CSD-based symmetric transpose block FIR implementation. : Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (巻 2017-October, pp. 311-314). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252475