A low power 720p motion estimation processor with 3D stacked memory

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto

研究成果: Conference contribution

抄録

In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the state-of-the-art MEP.

本文言語English
ホスト出版物のタイトルIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
出版社IEEE Computer Society
2015-January
January
DOI
出版ステータスPublished - 2015 1 7
イベント2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico
継続期間: 2014 10 62014 10 8

Other

Other2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
国/地域Mexico
CityPlaya del Carmen
Period14/10/614/10/8

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • ソフトウェア
  • 電子工学および電気工学

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