A low-power misprediction recovery mechanism

Jiongyao Ye, Takahiro Watanabe

研究成果: Conference contribution

抜粋

In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance. Previous researches proposed dual (or multi) path execution methods attempt to reduce the misprediction penalty, but these methods are quite complex and high power consumption. Most of the reasons are due to simultaneously fetching and executing instructions from multiple. In this paper, we reduce branch misprediction penalties based on the balance between complexity, power, and performance. We present a novel technique - Decode Recovery Cache (DRC) - for reducing misprediction penalty, giving consideration to complexity and power consumption simultaneously. The DRC stores decoded instructions that are mispredicted. Then during subsequent mispredictions, a hit in the DRC can reduce the re-fill time of pipeline, and eliminate instruction re-fetch and its subsequent decoding. The bypassing of both re-fetching and re-decoding reduces processor power. Experimental results employing SPECint 2000 benchmark show that, using a processor with DRC, IPC value is significantly improved by 10.4% on average over the traditional processors and average power consumption is reduced by 62.6%, compared with dual Path Instruction Processing.

元の言語English
ホスト出版物のタイトル1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
ページ209-212
ページ数4
DOI
出版物ステータスPublished - 2009 12 1
イベント1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 - Shanghai, China
継続期間: 2009 11 192009 11 21

出版物シリーズ

名前1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009

Conference

Conference1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
China
Shanghai
期間09/11/1909/11/21

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Education

フィンガープリント A low-power misprediction recovery mechanism' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。

  • これを引用

    Ye, J., & Watanabe, T. (2009). A low-power misprediction recovery mechanism. : 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 (pp. 209-212). [5397409] (1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009). https://doi.org/10.1109/PRIMEASIA.2009.5397409