A low power soft error hardened latch with schmitt-trigger-based C-Element

    研究成果: Article

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    To deal with the reliability issue caused by soft errors, this paper proposed a low power soft error hardened latch (SHC) design using a novel Schmitt-Trigger-based C-element for reliable low power applications. Unlike state-of-the-art soft error tolerant latches that are usually based on hardware redundancy with large area overhead and high power consumption, the proposed SHC latch is implemented through double-sampling and node-checking using a novel Schmitt-Trigger-based C-element, which can help to reduce the area overhead and the corresponding power consumption as well. The evaluation results show that the total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 20.35% and 82.96% power reduction can be achieved when compared to the conventional un-hardened C2MOS latch and the existing soft error tolerant HiPeR design, respectively.

    元の言語English
    ページ(範囲)1025-1034
    ページ数10
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E101A
    発行部数7
    DOI
    出版物ステータスPublished - 2018 7 1

    ASJC Scopus subject areas

    • Signal Processing
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering
    • Applied Mathematics

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