A low-power soft error tolerant latch scheme

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

    本文言語English
    ホスト出版物のタイトルProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
    出版社Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子版)9781479984831
    DOI
    出版ステータスPublished - 2016 7 19
    イベント11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
    継続期間: 2015 11 32015 11 6

    Other

    Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
    国/地域China
    CityChengdu
    Period15/11/315/11/6

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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