A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Qian Xie, Leona Okamura, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bit-iter.

    本文言語English
    ホスト出版物のタイトルProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    ページ298-301
    ページ数4
    DOI
    出版ステータスPublished - 2011
    イベント2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu
    継続期間: 2011 4 252011 4 28

    Other

    Other2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    CityHsinchu
    Period11/4/2511/4/28

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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