In the LTE-Advanced standards, to satisfy the low-power dissipation requirement in mobile scenarios, a decoder with small memory size has attracted extensive attention. By decomposing the trellis diagram of the adopted turbo code, this paper proposes a memory reduced decoding architecture based on reverse recalculation. A modified Jacobian logarithm is specially investigated for the reverse recalculation, and the reverse recalculation in logarithmic domain and the realization structure are also presented. It shows that at the price of low redundant calculation complexity, the memory size is reduced by 50%, while the decoding performance is very close to that of the Log-MAP algorithm. The proposed decoding scheme is superior to other decoding architectures in terms of dummy computation complexity, memory size and decoding performance.
|ジャーナル||Tien Tzu Hsueh Pao/Acta Electronica Sinica|
|出版ステータス||Published - 2017 7月 1|
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