A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard

Fan Yibo, Katto Jiro, Sun Heming, Zeng Xiaoyang, Zeng Yixuan

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Intelligent sensing is an important application field of video coding. For the next generation video coding standard Versatile Video Coding (VVC), several new contributions have been proposed to improve the coding efficiency, especially in the transformation operations. This paper proposes a unified transform architecture for VVC standard that enables 1D Discrete Sine Transform-VII (DST-VII) and Discrete Cosine Transform-VIII (DCT-VIII) of all sizes. In order to minimize the number of adders, the N-Dimensional Reduced Adder Graph (RAG-n) algorithm is adopted to design the logical computation of the VVC transforms. In addition, a pipeline operation is employed to achieve a high throughput rate of 32 samples per cycle. The experimental and synthesis results show that our proposal can save 16.96% area and 9.89% power consumption than the direct implementation by the multipliers. Moreover, this design can reduce the normalized area (NA) by at least 57.53% compared with other advanced works.

本文言語English
ホスト出版物のタイトルProceedings - 32nd IEEE International System on Chip Conference, SOCC 2019
編集者Danella Zhao, Arindam Basu, Magdy Bayoumi, Gwee Bah Hwee, Ge Tong, Ramalingam Sridhar
出版社IEEE Computer Society
ページ176-180
ページ数5
ISBN(電子版)9781728134826
DOI
出版ステータスPublished - 2019 9
イベント32nd IEEE International System on Chip Conference, SOCC 2019 - Singapore, Singapore
継続期間: 2019 9 32019 9 6

出版物シリーズ

名前International System on Chip Conference
2019-September
ISSN(印刷版)2164-1676
ISSN(電子版)2164-1706

Conference

Conference32nd IEEE International System on Chip Conference, SOCC 2019
CountrySingapore
CitySingapore
Period19/9/319/9/6

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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