A mixed design flow for FPGA prototyping of design with scan circuits

Lingfeng Li, Eko Fajar, Ken Ichi Kurimoto, Satoshi Goto

研究成果: Conference contribution

抄録

Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.

本文言語English
ホスト出版物のタイトルASICON 2005: 2005 6th International Conference on ASIC, Proceedings
ページ1031-1034
ページ数4
2
出版ステータスPublished - 2005
イベントASICON 2005: 2005 6th International Conference on ASIC - Shanghai
継続期間: 2005 10 242005 10 27

Other

OtherASICON 2005: 2005 6th International Conference on ASIC
CityShanghai
Period05/10/2405/10/27

ASJC Scopus subject areas

  • Engineering(all)

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