Scan circuits are utilized in our design to support some special functionalities besides test requirements, and thus they need to be inserted before the stage of function verification. In this paper, we propose a mixed design flow for field programmable gate array (FPGA) prototyping of the design with scan circuits. This mixed design flow combines the application specific integrated circuit (ASIC) design flow with typical FPGA design flow to implement automatically scan insertion. Experimental results show that this design flow functions well even for a complicated design, and only 2.5 % of the development time is required when compared to manual process.
|ホスト出版物のタイトル||ASICON 2005: 2005 6th International Conference on ASIC, Proceedings|
|出版ステータス||Published - 2005|
|イベント||ASICON 2005: 2005 6th International Conference on ASIC - Shanghai|
継続期間: 2005 10月 24 → 2005 10月 27
|Other||ASICON 2005: 2005 6th International Conference on ASIC|
|Period||05/10/24 → 05/10/27|
ASJC Scopus subject areas