抄録
Combining switched-capacitor technology with body effect in MOSFETs, a nano-power CMOS voltage reference is implemented in 0.18 μm standard CMOS technology. The low output breaking threshold restriction is produced without using any component subdivision, such that chip area is saved. Measurements show that the output voltage is about 123.3 mV, temperature coefficient is about 17.6 ppm/°C, and line sensitivity is 0.15 %/V. The supply current is less than 90 nA when the supply voltage is 1 V. The area occupation is about 0.03 mm2.
本文言語 | English |
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ホスト出版物のタイトル | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 |
DOI | |
出版ステータス | Published - 2013 |
イベント | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong 継続期間: 2013 6月 3 → 2013 6月 5 |
Other
Other | 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 |
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City | Hong Kong |
Period | 13/6/3 → 13/6/5 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学