A new 7-transistor SRAM cell design with high read stability

Yen Hsiang Tseng, Yimeng Zhang, Leona Okamura, Tsutomu Yoshihara

    研究成果: Conference contribution

    9 被引用数 (Scopus)

    抄録

    The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

    本文言語English
    ホスト出版物のタイトル2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings
    ページ43-47
    ページ数5
    DOI
    出版ステータスPublished - 2010
    イベント2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur
    継続期間: 2010 4 122010 4 13

    Other

    Other2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010
    CityKuala Lumpur
    Period10/4/1210/4/13

    ASJC Scopus subject areas

    • 電子工学および電気工学

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