The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.
|ホスト出版物のタイトル||2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings|
|出版ステータス||Published - 2010|
|イベント||2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010 - Kuala Lumpur|
継続期間: 2010 4 12 → 2010 4 13
|Other||2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA2010|
|Period||10/4/12 → 10/4/13|
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