A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM

Yasushi Terada, Kazuo Kobayashi, Takeshi Nakayama, Hideaki Arima, Tsutomu Yoshihara

研究成果: Article

4 引用 (Scopus)

抜粋

A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.

元の言語English
ページ(範囲)86-90
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
23
発行部数1
DOI
出版物ステータスPublished - 1988
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Terada, Y., Kobayashi, K., Nakayama, T., Arima, H., & Yoshihara, T. (1988). A New Architecture for the NVRAM-An EEPROM Backed-Up Dynamic RAM. IEEE Journal of Solid-State Circuits, 23(1), 86-90. https://doi.org/10.1109/4.261