A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki; Takeshi Nakayama; Shin ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara

doi:10.1109/4.126547

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

研究成果: Article › 査読

12 被引用数 (Scopus)

抄録

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

本文言語	English
ページ（範囲）	583-588
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	27
号	4
DOI	https://doi.org/10.1109/4.126547
出版ステータス	Published - 1992 4
外部発表	はい

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.126547

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引用スタイル

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AU - Miyawaki, Yoshikazu

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AU - Kobayashi, Shin ichi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

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