A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

研究成果: Article査読

12 被引用数 (Scopus)

抄録

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

本文言語English
ページ(範囲)583-588
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
27
4
DOI
出版ステータスPublished - 1992 4
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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