A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki; Takeshi Nakayama; Shin ichi Kobayashi; Natsuo Ajika; Makoto Ohi; Yasushi Terada; Hideaki Arima; Tsutomu Yoshihara

doi:10.1109/4.126547

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

Yoshikazu Miyawaki^*, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Article › 査読

12 被引用数 (Scopus)

抄録

To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

本文言語	English
ページ（範囲）	583-588
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	27
号	4
DOI	https://doi.org/10.1109/4.126547
出版ステータス	Published - 1992 4月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.126547

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@article{480ee52a4c5c46ec898e3f17871d584d,

title = "A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories",

abstract = "To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.",

author = "Yoshikazu Miyawaki and Takeshi Nakayama and Kobayashi, {Shin ichi} and Natsuo Ajika and Makoto Ohi and Yasushi Terada and Hideaki Arima and Tsutomu Yoshihara",

year = "1992",

month = apr,

doi = "10.1109/4.126547",

language = "English",

volume = "27",

pages = "583--588",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

AU - Miyawaki, Yoshikazu

AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1992/4

Y1 - 1992/4

N2 - To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

AB - To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.

UR - http://www.scopus.com/inward/record.url?scp=0026853679&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026853679&partnerID=8YFLogxK

U2 - 10.1109/4.126547

DO - 10.1109/4.126547

M3 - Article

AN - SCOPUS:0026853679

VL - 27

SP - 583

EP - 588

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

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