抄録
To improve the performance of high-density flash memories, several circuit technologies have been developed. A word-line boost and clamp scheme realizes low supply voltage read operations. A flash programming scheme utilizing Fowler-Nordheim (F-N) tunneling for programming before erasure and a negative gate biased erasing scheme accomplish low-power, high-speed, and 5-V-only erase operations. The chip size penalty is estimated to be only 3% for the 16-Mb flash memories.
本文言語 | English |
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ページ(範囲) | 583-588 |
ページ数 | 6 |
ジャーナル | IEEE Journal of Solid-State Circuits |
巻 | 27 |
号 | 4 |
DOI | |
出版ステータス | Published - 1992 4月 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学