A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

本文言語English
ホスト出版物のタイトル91 Symp VLSI Circuits
Place of PublicationPiscataway, NJ, United States
出版社Publ by IEEE
ページ85-86
ページ数2
出版ステータスPublished - 1991
外部発表はい
イベント1991 Symposium on VLSI Circuits - Oiso, Jpn
継続期間: 1991 5 301991 6 1

Other

Other1991 Symposium on VLSI Circuits
CityOiso, Jpn
Period91/5/3091/6/1

ASJC Scopus subject areas

  • 工学(全般)

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