A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

Yoshikazu Miyawaki, Takeshi Nakayama, Shin ichi Kobayashi, Natsuo Ajika, Makoto Ohi, Yasushi Terada, Hideaki Arima, Tsutomu Yoshihara

研究成果: Conference contribution

8 引用 (Scopus)

抄録

The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

元の言語English
ホスト出版物のタイトル91 Symp VLSI Circuits
出版場所Piscataway, NJ, United States
出版者Publ by IEEE
ページ85-86
ページ数2
出版物ステータスPublished - 1991
外部発表Yes
イベント1991 Symposium on VLSI Circuits - Oiso, Jpn
継続期間: 1991 5 301991 6 1

Other

Other1991 Symposium on VLSI Circuits
Oiso, Jpn
期間91/5/3091/6/1

Fingerprint

Decoding
Electric potential
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Miyawaki, Y., Nakayama, T., Kobayashi, S. I., Ajika, N., Ohi, M., Terada, Y., ... Yoshihara, T. (1991). A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. : 91 Symp VLSI Circuits (pp. 85-86). Piscataway, NJ, United States: Publ by IEEE.

A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. / Miyawaki, Yoshikazu; Nakayama, Takeshi; Kobayashi, Shin ichi; Ajika, Natsuo; Ohi, Makoto; Terada, Yasushi; Arima, Hideaki; Yoshihara, Tsutomu.

91 Symp VLSI Circuits. Piscataway, NJ, United States : Publ by IEEE, 1991. p. 85-86.

研究成果: Conference contribution

Miyawaki, Y, Nakayama, T, Kobayashi, SI, Ajika, N, Ohi, M, Terada, Y, Arima, H & Yoshihara, T 1991, A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. : 91 Symp VLSI Circuits. Publ by IEEE, Piscataway, NJ, United States, pp. 85-86, 1991 Symposium on VLSI Circuits, Oiso, Jpn, 91/5/30.
Miyawaki Y, Nakayama T, Kobayashi SI, Ajika N, Ohi M, Terada Y その他. A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. : 91 Symp VLSI Circuits. Piscataway, NJ, United States: Publ by IEEE. 1991. p. 85-86
Miyawaki, Yoshikazu ; Nakayama, Takeshi ; Kobayashi, Shin ichi ; Ajika, Natsuo ; Ohi, Makoto ; Terada, Yasushi ; Arima, Hideaki ; Yoshihara, Tsutomu. / A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs. 91 Symp VLSI Circuits. Piscataway, NJ, United States : Publ by IEEE, 1991. pp. 85-86
@inproceedings{62f62c45c62443a9a22eb03fc8f130d2,
title = "A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs",
abstract = "The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.",
author = "Yoshikazu Miyawaki and Takeshi Nakayama and Kobayashi, {Shin ichi} and Natsuo Ajika and Makoto Ohi and Yasushi Terada and Hideaki Arima and Tsutomu Yoshihara",
year = "1991",
language = "English",
pages = "85--86",
booktitle = "91 Symp VLSI Circuits",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - A new erasing and row decoding scheme for low supply voltage operation 16 Mb/64 Mb flash EEPROMs

AU - Miyawaki, Yoshikazu

AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Terada, Yasushi

AU - Arima, Hideaki

AU - Yoshihara, Tsutomu

PY - 1991

Y1 - 1991

N2 - The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

AB - The authors describe a boosted word line decoding scheme for read operation at low supply voltage and negative gate biased erasing and flash programming for high-speed 5 V only erasing. Circuit technologies for 16 Mb/64 Mb flash EEPROM are proposed. The flash programming and negative gate biased erasing achieves low power, high speed and 5 V only erase operation. The chip size penalty is estimated to be only 3 percent for the 16 Mb flash EEPROM.

UR - http://www.scopus.com/inward/record.url?scp=0026372198&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026372198&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0026372198

SP - 85

EP - 86

BT - 91 Symp VLSI Circuits

PB - Publ by IEEE

CY - Piscataway, NJ, United States

ER -