A new hardware/software partitioning algorithm for DSP processor cores with two types of register files

Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohsuki

研究成果: Letter

抜粋

This letter proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more types of functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which consider only type of functional units for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

元の言語English
ページ(範囲)2802-2807
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E84-A
発行部数11
出版物ステータスPublished - 2001 11

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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