In this paper a new low power BIST methodology by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo-random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the non-detecting vectors by altering the structure of LFSR. Note that altering the structure of LFSR is efficient, and its has no impact on the fault coverage.
|出版ステータス||Published - 2001|
|イベント||4th International Conference on ASIC Proceedings - Shanghai, China|
継続期間: 2001 10月 23 → 2001 10月 25
|Conference||4th International Conference on ASIC Proceedings|
|Period||01/10/23 → 01/10/25|
ASJC Scopus subject areas