A new self-test structure for at-speed test of crosstalk in SoC busses

Jun Yang, Chen Hu, Youhua Shi, Zhe Zhang, Longxing Shi

研究成果: Paper

1 引用 (Scopus)

抜粋

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

元の言語English
ページ633-636
ページ数4
出版物ステータスPublished - 2001 12 1
イベント4th International Conference on ASIC Proceedings - Shanghai, China
継続期間: 2001 10 232001 10 25

Conference

Conference4th International Conference on ASIC Proceedings
China
Shanghai
期間01/10/2301/10/25

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Yang, J., Hu, C., Shi, Y., Zhang, Z., & Shi, L. (2001). A new self-test structure for at-speed test of crosstalk in SoC busses. 633-636. 論文発表場所 4th International Conference on ASIC Proceedings, Shanghai, China.