A new self-test structure for at-speed test of crosstalk in SoC busses

Jun Yang, Chen Hu, Youhua Shi, Zhe Zhang, Longxing Shi

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.

本文言語English
ページ633-636
ページ数4
出版ステータスPublished - 2001
外部発表はい
イベント4th International Conference on ASIC Proceedings - Shanghai, China
継続期間: 2001 10 232001 10 25

Conference

Conference4th International Conference on ASIC Proceedings
国/地域China
CityShanghai
Period01/10/2301/10/25

ASJC Scopus subject areas

  • 工学(全般)

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