A new software for test logic optimization in DFT

Zhe Zhang, Chen Hu, Rui Li, Youhua Shi, Longxing Shi

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

本文言語English
ページ654-657
ページ数4
出版ステータスPublished - 2001 12 1
外部発表はい
イベント4th International Conference on ASIC Proceedings - Shanghai, China
継続期間: 2001 10 232001 10 25

Conference

Conference4th International Conference on ASIC Proceedings
CountryChina
CityShanghai
Period01/10/2301/10/25

ASJC Scopus subject areas

  • Engineering(all)

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