A non-iterative effective capacitance model for CMOS gate delay computing

Minglu Jiang, Qiang Li, Zhangcai Huang, Yasuaki Inoue

    研究成果: Conference contribution

    抄録

    In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance G ef f which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Gef f equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Gef f calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

    本文言語English
    ホスト出版物のタイトル2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
    ページ896-900
    ページ数5
    DOI
    出版ステータスPublished - 2010
    イベント2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Chengdu
    継続期間: 2010 7 282010 7 30

    Other

    Other2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
    CityChengdu
    Period10/7/2810/7/30

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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