抄録
This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.
本文言語 | English |
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ホスト出版物のタイトル | ISOCC 2012 - 2012 International SoC Design Conference |
ページ | 17-20 |
ページ数 | 4 |
DOI | |
出版ステータス | Published - 2012 |
イベント | 2012 International SoC Design Conference, ISOCC 2012 - Jeju Island 継続期間: 2012 11 4 → 2012 11 7 |
Other
Other | 2012 International SoC Design Conference, ISOCC 2012 |
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City | Jeju Island |
Period | 12/11/4 → 12/11/7 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering