A novel charge recovery logic structure with complementary pass-transistor network

Jingyang Li*, Yimeng Zhang, Tsutomu Yoshihara

*この研究の対応する著者

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18μm process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50MHz to 500MHz and dissipates about 40% energy with respect to CPAL at 200MHz.

    本文言語English
    ホスト出版物のタイトルISOCC 2012 - 2012 International SoC Design Conference
    ページ17-20
    ページ数4
    DOI
    出版ステータスPublished - 2012
    イベント2012 International SoC Design Conference, ISOCC 2012 - Jeju Island
    継続期間: 2012 11 42012 11 7

    Other

    Other2012 International SoC Design Conference, ISOCC 2012
    CityJeju Island
    Period12/11/412/11/7

    ASJC Scopus subject areas

    • ハードウェアとアーキテクチャ
    • 電子工学および電気工学

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