A novel hardware method to implement a routing algorithm onto network on chip

Yiping Dong, Hua Zhang, Zhen Lin, Takahiro Watanabe

研究成果: Conference contribution

抜粋

Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate the router and NoC with proposed method in terms of circuit resource, latency and throughput. The results indicate that the NoC architecture with proposed method is effective in reducing circuit resource, latency and increasing throughput.

元の言語English
ホスト出版物のタイトル2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings
ページ852-856
ページ数5
DOI
出版物ステータスPublished - 2010 11 19
イベント2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Chengdu, China
継続期間: 2010 7 282010 7 30

出版物シリーズ

名前2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings

Conference

Conference2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010
China
Chengdu
期間10/7/2810/7/30

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • これを引用

    Dong, Y., Zhang, H., Lin, Z., & Watanabe, T. (2010). A novel hardware method to implement a routing algorithm onto network on chip. : 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings (pp. 852-856). [5581857] (2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings). https://doi.org/10.1109/ICCCAS.2010.5581857