A novel model for computing the effective capacitance of CMOS gates with interconnect loads

Zhangcai Huang*, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao

*この研究の対応する著者

    研究成果: Article査読

    6 被引用数 (Scopus)

    抄録

    In deep submicron designs, the interconnect wires play a major role in the timing behavior of logic gates. The effective capacitance Ceff concept is usually used to calculate the delay of gate with interconnect loads. In this paper, we present a new method of Integration Approximation to calculate Ceff. In this new method, the complicated nonlinear gate output is assumed as a piecewise linear (PWL) waveform. A new model is then derived to compute the value of Ceff. The introduction of Integration Approximation results in Ceff being insensitive to output waveform shape. Therefore, the new method can be applied to various output waveforms of CMOS gates with RC-π loads. Experimental results show a significant improvement in accuracy.

    本文言語English
    ページ(範囲)2562-2568
    ページ数7
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E88-A
    10
    DOI
    出版ステータスPublished - 2005 10月

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • ハードウェアとアーキテクチャ
    • 情報システム

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