A novel parasitic-aware synthesis and verification flow for RFIC desien

Wang Xuejin, Stephen McCracken, Aykut Dengi, Koji Takinami, Takayuki Tsukizawa, Yasunori Miyahara

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

The design of radio-frequency integrated circuits (RFICs) is highly sensitive to layout parasitics. In conventional methodologies, the layout parasitics are known only after the layout is complete and the schematic is resized to compensate for these parasitics. The drawback of such a methodology is that the convergence of this design iteration remains unpredictable. This paper proposes a novel synthesis and verification flow for RFIC designs. The design flow is composed of three stages: circuit sizing with floorplan, performance-aware floorplan refinement, and full-wave electromagnetic (EM) extraction. Layout parasitics are considered throughout the design flow in the proposed methodology. As a result, parasitic closure can be achieved quickly and design iterations may not be required. As an example, the proposed design flow is applied to a crosscoupled inductance-capacitance (LC) VCO. Demonstrating the efficiency of the proposed flow for RFIC designs, it required only two weeks to meet all the design specifications with no iterations.

本文言語English
ホスト出版物のタイトルProceedings of the 36th European Microwave Conference, EuMC 2006
出版社IEEE Computer Society
ページ664-667
ページ数4
ISBN(印刷版)2960055160, 9782960055160
DOI
出版ステータスPublished - 2006
外部発表はい
イベント36th European Microwave Conference, EuMC 2006 - Manchester, United Kingdom
継続期間: 2006 9 102006 9 12

出版物シリーズ

名前Proceedings of the 36th European Microwave Conference, EuMC 2006

Conference

Conference36th European Microwave Conference, EuMC 2006
CountryUnited Kingdom
CityManchester
Period06/9/1006/9/12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Radiation

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