A novel process for fabrication of gated silicon field emitter array taking advantage of ion bombardment retarded etching

Takashi Tanii*, Satoru Fujita, Yoshiteru Numao, Iwao Matsuya, Mitsuaki Sakairi, Meishoku Masahara, Iwao Ohdomari

*この研究の対応する著者

研究成果: Article査読

2 被引用数 (Scopus)

抄録

A novel process for the fabrication of a gated silicon field emitter array is proposed. The process involves complete self-alignment of gate electrodes taking advantage of ion bombardment retarded etching. The ion-irradiated regions serve as masks for subsequent silicon etching resulting in the formation of tabletop structures. The structures are suitable for both the formation of pyramidal emitters and the arrangement of gate electrodes adjacent to each emitter. We integrate this silicon etching into a self-align process for the fabrication of gated emitter array. The emission characteristics of 100 emitters are tested, and the emission at a gate voltage of 30 V is detected. The results indicate that the proposed process is applicable to the fabrication of gated silicon emitters.

本文言語English
ページ(範囲)5191-5192
ページ数2
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
44
7 A
DOI
出版ステータスPublished - 2005 7 8

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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