A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.
|ホスト出版物のタイトル||1st International Conference on Green Circuits and Systems, ICGCS 2010|
|出版ステータス||Published - 2010|
|イベント||1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai|
継続期間: 2010 6月 21 → 2010 6月 23
|Other||1st International Conference on Green Circuits and Systems, ICGCS 2010|
|Period||10/6/21 → 10/6/23|
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