A novel structure of energy efficiency charge recovery logic

Yimeng Zhang, Leona Okamura, Mengshu Huang, Tsutomu Yoshihara

    研究成果: Conference contribution

    6 被引用数 (Scopus)

    抄録

    A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a highspeed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

    本文言語English
    ホスト出版物のタイトル1st International Conference on Green Circuits and Systems, ICGCS 2010
    ページ133-136
    ページ数4
    DOI
    出版ステータスPublished - 2010
    イベント1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai
    継続期間: 2010 6 212010 6 23

    Other

    Other1st International Conference on Green Circuits and Systems, ICGCS 2010
    CityShanghai
    Period10/6/2110/6/23

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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