A parallel LSI architecture for LDPC decoder improving message-passing schedule

Kazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

7 引用 (Scopus)

抜粋

This paper proposes a parallel LSI architecture for LDPC decoder which improves a message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently, (ii) The proposed parallel pipelined bit functional unit enables the decoder to perform every column operation using the messages which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay. Hardware implementation and simulation results show that the proposed decoder improves the decoding throughput and bit error performance with a small hardware overhead.

元の言語English
ホスト出版物のタイトルISCAS 2006
ホスト出版物のサブタイトル2006 IEEE International Symposium on Circuits and Systems, Proceedings
ページ5099-5102
ページ数4
出版物ステータスPublished - 2006 12 1
イベントISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
継続期間: 2006 5 212006 5 24

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷物)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Greece
Kos
期間06/5/2106/5/24

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Shimizu, K., Ishikawa, T., Togawa, N., Ikenaga, T., & Goto, S. (2006). A parallel LSI architecture for LDPC decoder improving message-passing schedule. : ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 5099-5102). [1693779] (Proceedings - IEEE International Symposium on Circuits and Systems).