A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

抄録

In this paper, we propose a partial redundant fault-secure high-level synthesis algorithm for RDR architectures, where we duplicate a part of the original CDFG and maximize its reliability under a timing constraint. Firstly, our algorithm allocates some new additional functional units to vacant spaces on RDR islands for recomputation and increases the number of duplicated operation nodes. Secondly, it minimizes the number of inserted comparator nodes through re-scheduling/re-binding the recomputation CDFG's nodes. As a result, we will obtain a scheduled/bound recomputation CDFG and renewed functional unit allocation with high reliability. Experimental results demonstrate that our algorithm improves reliability by up to 52% compared with the conventional approach.

本文言語English
ホスト出版物のタイトル2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
ページ1736-1739
ページ数4
DOI
出版ステータスPublished - 2013
イベント2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
継続期間: 2013 5 192013 5 23

出版物シリーズ

名前Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(印刷版)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
国/地域China
CityBeijing
Period13/5/1913/5/23

ASJC Scopus subject areas

  • 電子工学および電気工学

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